This patch adds id_reg_info for ID_DFR0_EL1 to make it writable
by userspace.
Return an error if userspace tries to set PerfMon field of the
register to a value that conflicts with the PMU configuration.
Signed-off-by: Reiji Watanabe <rei...@google.com>
---
arch/arm64/kvm/sys_regs.c | 57 +++++++++++++++++++++++++++++++--------
1 file changed, 46 insertions(+), 11 deletions(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 61e61f4bb81c..84c064dfc63a 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -442,6 +442,25 @@ static int validate_id_aa64dfr0_el1(struct kvm_vcpu *vcpu,
u64 val)
return 0;
}
+static int validate_id_dfr0_el1(struct kvm_vcpu *vcpu, u64 val)
+{
+ bool vcpu_pmu = kvm_vcpu_has_pmu(vcpu);
+ unsigned int perfmon = cpuid_feature_extract_unsigned_field(val,
+ ID_DFR0_PERFMON_SHIFT);
+ bool dfr0_pmu = id_reg_has_pmu(val, ID_DFR0_PERFMON_SHIFT,
+ ID_DFR0_PERFMON_8_0);
+
+ if (perfmon == 1 || perfmon == 2)
+ /* PMUv1 or PMUv2 is not allowed on ARMv8. */
+ return -EINVAL;
+
+ /* Check if there is a conflict with a request via KVM_ARM_VCPU_INIT */
+ if (vcpu_pmu ^ dfr0_pmu)
+ return -EPERM;
+
+ return 0;
+}
+
static void init_id_aa64pfr0_el1_info(struct id_reg_info *id_reg)
{
u64 limit;
@@ -526,6 +545,16 @@ static void init_id_aa64dfr0_el1_info(struct id_reg_info
*id_reg)
id_reg->vcpu_limit_val = limit;
}
+static void init_id_dfr0_el1_info(struct id_reg_info *id_reg)
+{
+ id_reg->sys_val = read_sanitised_ftr_reg(id_reg->sys_reg);
+
+ /* Limit guests to PMUv3 for ARMv8.4 */
+ id_reg->vcpu_limit_val = id_reg_cap_pmu(id_reg->sys_val,
+ ID_DFR0_PERFMON_SHIFT,
+ ID_DFR0_PERFMON_8_4);
+}
+
static u64 get_reset_id_aa64pfr0_el1(struct kvm_vcpu *vcpu,
struct id_reg_info *idr)
{
@@ -557,6 +586,14 @@ static u64 get_reset_id_aa64dfr0_el1(struct kvm_vcpu *vcpu,
(idr->vcpu_limit_val &
~(ARM64_FEATURE_MASK(ID_AA64DFR0_PMUVER)));
}
+static u64 get_reset_id_dfr0_el1(struct kvm_vcpu *vcpu,
+ struct id_reg_info *idr)
+{
+ return kvm_vcpu_has_pmu(vcpu) ?
+ idr->vcpu_limit_val :
+ (idr->vcpu_limit_val & ~(ARM64_FEATURE_MASK(ID_DFR0_PERFMON)));
+}
+
static struct id_reg_info id_aa64pfr0_el1_info = {
.sys_reg = SYS_ID_AA64PFR0_EL1,
.init = init_id_aa64pfr0_el1_info,
@@ -593,6 +630,13 @@ static struct id_reg_info id_aa64dfr0_el1_info = {
.get_reset_val = get_reset_id_aa64dfr0_el1,
};
+static struct id_reg_info id_dfr0_el1_info = {
+ .sys_reg = SYS_ID_DFR0_EL1,
+ .init = init_id_dfr0_el1_info,
+ .validate = validate_id_dfr0_el1,
+ .get_reset_val = get_reset_id_dfr0_el1,
+};
+
/*
* An ID register that needs special handling to control the value for the
* guest must have its own id_reg_info in id_reg_info_table.
@@ -602,6 +646,7 @@ static struct id_reg_info id_aa64dfr0_el1_info = {
*/
#define GET_ID_REG_INFO(id) (id_reg_info_table[IDREG_IDX(id)])
static struct id_reg_info *id_reg_info_table[KVM_ARM_ID_REG_MAX_NUM] = {
+ [IDREG_IDX(SYS_ID_DFR0_EL1)] = &id_dfr0_el1_info,
[IDREG_IDX(SYS_ID_AA64PFR0_EL1)] = &id_aa64pfr0_el1_info,
[IDREG_IDX(SYS_ID_AA64PFR1_EL1)] = &id_aa64pfr1_el1_info,
[IDREG_IDX(SYS_ID_AA64DFR0_EL1)] = &id_aa64dfr0_el1_info,
@@ -1440,18 +1485,8 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu,
struct sys_reg_desc const *r, bool raz)
{
u32 id = reg_to_encoding(r);
- u64 val = raz ? 0 : __vcpu_sys_reg(vcpu, IDREG_SYS_IDX(id));
- switch (id) {
- case SYS_ID_DFR0_EL1:
- /* Limit guests to PMUv3 for ARMv8.4 */
- val = cpuid_feature_cap_perfmon_field(val,
- ID_DFR0_PERFMON_SHIFT,
- kvm_vcpu_has_pmu(vcpu) ?
ID_DFR0_PERFMON_8_4 : 0);
- break;
- }
-
- return val;
+ return raz ? 0 : __vcpu_sys_reg(vcpu, IDREG_SYS_IDX(id));
}
static unsigned int id_visibility(const struct kvm_vcpu *vcpu,
--
2.33.0.882.g93a45727a2-goog
_______________________________________________
kvmarm mailing list
kvmarm@lists.cs.columbia.edu
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
