Re: Testing Fiasco.OC+L4re on ODROID-X2(Exynos4412)

Thu, 11 Jun 2015 14:15:56 -0700 

Hi Adam

On 06/11/2015 04:39 PM, Adam Lackorzynski wrote:

Hi,

On Thu Jun 04, 2015 at 23:56:15 -0400, Reinier Millo Sánchez wrote:

We have adapted the Proc class to support the IRQ on Fiasco.OC when
compiling it in TrustZone Normal Side. Following the principle that in
TrustZone the IRQ are used on Normal Side and the FIQ are used in Secure
Side, we have only used the IRQ when compile the Fiasco.OC with TrustZone
Normal Side. By default Fiasco.OC was using the IRQ and FIQ when compiling
with TrustZone Normal Side. This is our patch:

True that on normal side only the FIQ is used, but the FIQ state shall
not play a role there, as the normal side must not be able to interfere
with the secure side. So it shouldn't matter?
The normal side must not interfere with secure side. The normal side only use the IRQ and secure side the FIQ. By default when not using TrustZone Secure Side, Fiasco.OC try to enable both interrupts, the IRQ and FIQ. We think that there is a problem, when the kernel running on normal side try to write the FIQ bit. In this case we think that the operation is cancelled and the IRQ remains deactivated too. The current implementation of Fiasco.OC make a diference only in TrustZone Secure Side, and only activates the FIQ. We adapted the Proc class to activate only the IRQ when compiling FiascoOC on TrustZone Normal Side with a Secure Monitor Interface. In this case the FIQ bit is not write and the operation isn't cancelled. 


Now when we compile Fiasco.OC and run the Hello example for Odroid-X2 using
TrustZone Normal Side, it works fine.

Ok good. What is running on the secure side in this case?

In this case we have nothing running on secure side.



We have noted the when is compiled with TrustZone Secure Side, then only use
the FIQ, but when try to run it on Odroid-X2 it fails. This is the serial
output:

    GIC: Switching IRQ 64 to secure
    GIC: Switching IRQ 79 to secure
    GIC: Switching IRQ 78 to secure
    GIC: Switching IRQ 9 to secure
    GIC: Switching IRQ 8 to secure
    GIC: Switching IRQ 10 to secure
    GIC: Switching IRQ 11 to secure

Did you try to figure out where it is stuck?
In this case we have only tested the simple configuration. We have seen that to run a example with TrustZone Secure Side, seems to be a little more complex. Now we are trying to test de vmm's example. 


We are also interested to use Fiasco.OC for ODROID-X2 without TrustZone, in
which case we must configure both IRQ and FIQ, but fails. This the serial
output:

Is that the 'std' mode? I.e. there's nothing running on the secure side?
This is standard mode without trustzone. The FiascoOC is configured in standard mode. I have been looking for information about the trustzone, this is a security mechanism provided by hardware. But, there is any way to use the hardware without trustzone, or it must be used always on normal or secure side? 


    Regions of list 'regions'
         [ 40000000,  400000e3] {       e4} Root   mbi_rt
         [ 40001000,  40001aff] {      b00} Kern   fiasco
         [ 40002000,  4003afff] {    39000} Kern   fiasco
         [ 40090000,  4009681b] {     681c} Sigma0 sigma0
         [ 40098000,  4009e177] {     6178} Sigma0 sigma0
         [ 40140000,  4018b4ab] {    4b4ac} Root   moe
         [ 41000000,  4100e4ff] {     e500} Boot   bootstrap
         [ 41100000,  41133fff] {    34000} Root   Module
       API Version: (87) experimental
       Sigma0 config    ip:40090100 sp:00000000
       Roottask config  ip:4014020c sp:00000000
       Starting kernel fiasco at 400012c8
    Hello from Startup::stage2
    Per_cpu_data_alloc: (orig: 0xf002d7a0-0xf002e1a8)
    Number of IRQs available at this GIC: 160
    FPU0: Arch: VFPv3(3), Part: VFPv3(30), r: 4, v: 9, i: 41, t: hard,
    p: dbl/sngl

    KERNEL: Warning: No page-fault handler for 0xee202108, error
    0x94000848, pc f002660c

Anyone know what is happening with interrupts in Exynos4412 when TrustZone
is not used? Anyone have some idea?



Adam

Best regards

--
Lic. Reinier Millo Sánchez
Centro de Estudios de Informática
Universidad Central "Marta Abreu" de Las Villas
Carretera a Camajuaní Km 5 1/2
Santa Clara, Villa Clara, Cuba
CP 54830

"antes de discutir ... respira;
  antes de hablar ... escucha;
 antes de escribir ... piensa;
  antes de herir ... siente;
 antes de rendirte ... intenta;
  antes de morir ... vive"

<<attachment: rmillo.vcf>>

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