On Wed, 2014-05-14 at 10:27 +0200, Gwenole Beauchesne wrote: > Hi, > > 2014-05-14 10:10 GMT+02:00 Zhao, Yakui <yakui.z...@intel.com>: > > On Wed, 2014-05-14 at 01:47 -0600, Gwenole Beauchesne wrote: > >> The MI_FLUSH_DW command contains 5 dwords on Broadwell, i.e. one extra > >> dword for the high order bits of the Address field. > > > > Thanks for your patch. > > > > What is wrong if this is applied? > > The 4 dwords are still ok to Broadwell. And the address/data field are > > not used in the command of MI_FLUSH_DW. > > So the current command is correct for Broadwell. > > Yes, it's still correct... until we use post-sync ops. But anyway, if > you want to keep at the minimum similar semantics to what used to be > used, then it's preferred to have the required provisions for handling > that. Before, we used the defaults (QWORD immediate, if any). Now, the > default semantics changed. > > (Un)fortunately, a command stream verifier won't notice that, but if > you want to strictly implement the specs for consistency, an Address > is always 64-bits on Broadwell. If you don't want to follow the specs, > that's your call, just remember that in the future and update the code > accordingly.
Thanks for your reminder. As Haihao mentioned, currently we don't use the post-sync ops. In such case the 4 or 5 dwords follow the spec for BDW. In fact there is no post-sync operation, QW/DW doesn't matter. If the post-sync is essential/required, we will take care of updating the code in future. Thanks. Yakui > > Regards, > Gwenole. > > >> --- > >> src/intel_batchbuffer.c | 7 +++++-- > >> 1 file changed, 5 insertions(+), 2 deletions(-) > >> > >> diff --git a/src/intel_batchbuffer.c b/src/intel_batchbuffer.c > >> index bc564d5..01e04d5 100644 > >> --- a/src/intel_batchbuffer.c > >> +++ b/src/intel_batchbuffer.c > >> @@ -247,13 +247,16 @@ intel_batchbuffer_emit_mi_flush(struct > >> intel_batchbuffer *batch) > >> } > >> > >> } else { > >> + const uint32_t extra_dword = !!IS_GEN8(intel->device_id); > >> uint32_t cmd = MI_FLUSH_DW; > >> if (batch->flag == I915_EXEC_BSD) > >> cmd |= MI_FLUSH_DW_VIDEO_PIPELINE_CACHE_INVALIDATE; > >> > >> - __BEGIN_BATCH(batch, 4, batch->flag); > >> - __OUT_BATCH(batch, cmd); > >> + __BEGIN_BATCH(batch, 4|extra_dword, batch->flag); > >> + __OUT_BATCH(batch, cmd|extra_dword); > >> __OUT_BATCH(batch, 0); > >> + if (extra_dword) > >> + __OUT_BATCH(batch, 0); > >> __OUT_BATCH(batch, 0); > >> __OUT_BATCH(batch, 0); > >> __ADVANCE_BATCH(batch); > > > > _______________________________________________ Libva mailing list Libva@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/libva