Hi all, I have been wondering why the SDRAM in Assabet has 14 row address bits configured in the blob and bootldr. The SDRAM used in Assabet has only 12 row address bits and 9 column address bits. To find out I changed the rows to 12 and followed the SDRAM controller intialization procedure given in Fig 10-7. Assumptions 1. The address given to the SDRAM controller is A0-A25 2. The column address sent to the SDRAM by the controller is CA0-CA7
After initializing I ran a memory test on the SDRAM. Here I wrote the memory's address in the memory location. This I repeated for every 1K. That is 1. load r0 with 0xc0000000 2. Store r0 in the location pointed to by r0(str r0,[r0]) 3. Increment r0 by 1K 4. Repeat steps 2 and 3 until r0 equals 0xc2000000 Then read the contents back in the same order. When I ran the above test with 14 row address bits the test ran successfully. When I ran it with 12 rows I got the memory failure at 0xc0000000 which had 0xc1000000. Then I ran the above test for just 16 Mb only and it ran successfully. The reaaon for this is table 10-7. The SDRAM in Assabet has 9 column bitsand 12 row bits. This means each row is 512 colums and since each column is 32 bit the size of a single row is 2k bytes. The lines from the processor going to SDRAM from the processor are A10-A24. Since we have configured for 14 row address bits the lines A10-A23 will be taken as rows by the SDRAM controller inside the processor and given to the SDRAM as the row address. Here A24 is excluded. The SDRAM requires only 12 row address bits hence it takes only A10-A21. The A22 and A23 are wired as bank selects. Now when the column address is given to the SDRAM from the controller, A24 is given as column address CA8 and A2-A9 are given as the other 8 column addresses CA0-CA7. (Reference table 10-7 configuration 14 bits). Since the A24 bit gets set only after 16 MB only 256 columns of each row are accessed. That is in each row the first 256 columns are meant for addresses within the range 0-16 MB and the other 256 columns are in the range 16-32 MB. But when we configure it as 12 row address bits the A22 pin is given as CA8. For every 4 MB the A22 pin toggles and is the same from 1-4MB and from 16-20 MB. That is the same 256 columns are again accessed when read after 16Mb . Thus there is overlapping. For Strong ARM configurations which use only 16 MB RAM that has 4096 rows and 256 columns * 2 (chips per bank) can set the row address bits as 12 and it should work correctly as per the above argument. If this is already a well known fact please excuse me. I thought I can share this with others. Harishankkar _______________________________________________ http://lists.arm.linux.org.uk/mailman/listinfo/linux-arm Please visit the above address for information on this list.
