Russell King - ARM Linux Admin wrote:
> Dave Baukus writes:
> > Stephen Noftall wrote:
> > > I just heard from Intel that they are coming out with a new SA-110, that
> > > supposedly fixes a bug only found in demand paged memory management OS's. The
> > > new part numbers are 21281-xB.
> >
> >
> > Any know the real answer ?
>
> Any program in a demand paged OS would be susceptible to this problem. However,
> The Linux kernel itself is not. The routines which use the ldm instruction are
> carefully coded to handle the user space permissions anyway, so a ldm instruction
> is never used to cross a page boundary.
>
> It is, however, an issue for user programs. The user stack is a conventional
> full decending stack, which means that the affected instruction (ldmib) will not
> be used.
>
> Hence, I think the answer to this is that the ARM Linux OS is not susceptible
> to this problem, but user programs could be. My current experiance suggests that
> no user programs currently exist which hit this problem.
> _____
I concur with Russell's statements.
We received Intel's errata in July. At that time, I investigated both the
code build environment, and the existing binary code. I, too, concentrated on
the kernel itself. In both cases, Russell is correct. [Of course he is; he wrote the
relevent code!]
I am not at all concerned with the existence of this errata, in terms of existing
code, and code which is being written. [ArmLinux only]
However, if people want to persue an experimental attack on SA-110 systems
to see where they break, I think that is a good idea.
BTW, someone asked about how do you tell chip rev numbers? The chip ID register
will return a 3 for S steppings (the ones that exhibit the errata). I have never seen
a T stepping (the new ones), but I assume the chip ID register will be incremented.
Pat
CorelComputer/HCC
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