Russell King - ARM Linux Admin writes:
> Philip Blundell writes:
> > It sounds like the 21285 is trying to perform some transaction on the bus
> > either to satisfy a read or to unload its write FIFO (and it's stalled the
> > SA110 while it does so) but it keeps getting a retry response. Can you
> > examine the PCI bus and see what's going on in terms of the address that the
> > Footbridge asserts and the response it gets from the target?
>
> I'll try, but all my slots are full, and I can only get to the 'B' side
> of the PCI connectors safely. This means that I can get to all but
> CBE0, STOP, SDONE and TRDY signals. I'll also reduce the bus speed
> to make it easier on the poor 60MHz scope...
Indeed yes, the SA110 this time was trying to do a PCI IACK cycle, however
the DC21285 was attempting to perform some operation at PCI address 0x21
(Control bits 0011, whatever that means), but getting retry responses from
the Southbridge.
There is a bit in the PCI config space - index 0x44, bit 4, which is
described as:
Retry on excessive delay control:
0: Disable retry if delay will be longer than 16 PCI clock cycles
1: Enable retry if delay will be longer than 16 PCI clock cycles
(Rev. 2.1 Compliant)
If I set this bit, then the bus locks in endless retry mode. However,
if I clear this bit, then the bus seems to lock with the Southbridges
bus request and bus grant permanently active, however it did (on my
single attempt) get slightly further. There appears to be no DMA
active (since I don't hear anything unlike before), so I guess that
the PCI bus is stagnant.
The Southbridge doesn't seem to have a latency timer on it, nor any other
timing-related registers - it just seems to have regs 0, 2, 4, 6, 8,
9, A, B and E apart from the manufacturer specific regs at 0x40 and
above. Naturally for DMA, it has the normal PC DMA register set.
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