>Indeed yes, the SA110 this time was trying to do a PCI IACK cycle, however
>the DC21285 was attempting to perform some operation at PCI address 0x21
>(Control bits 0011, whatever that means), but getting retry responses from
>the Southbridge.
Command 0011 is an I/O write, and of course ISA I/O address 0x21 is the
first PIC. Since IACK is a read cycle it almost certainly requires the
outbound FIFO to be flushed.
>if I clear this bit, then the bus seems to lock with the Southbridges
>bus request and bus grant permanently active, however it did (on my
>single attempt) get slightly further. There appears to be no DMA
It's hard to say what happens in this case. From the description you've given
of the control bit, I'd expect the lock-up to occur with the 21285 having bus
ownership (because it sits waiting for a TRDY that never comes; the latency
timer doesn't really protect you against this case).
>The Southbridge doesn't seem to have a latency timer on it, nor any other
>timing-related registers - it just seems to have regs 0, 2, 4, 6, 8,
>9, A, B and E apart from the manufacturer specific regs at 0x40 and
>above. Naturally for DMA, it has the normal PC DMA register set.
It may well not have a latency timer if it's not capable of burst transfers.
Even if it did, it wouldn't help in either of the failure modes you're seeing
-- in the first one you described, the southbridge is correctly relinquishing
the bus anyway, and in the second one the arbiter isn't removing its GNT so
the latency timer would have no effect.
Does the documentation or errata for the southbridge say anything about the
circumstances under which it responds with retry to target write transactions?
p.
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