Philip Blundell writes:
> What do you estimate the slowdown would be from introducing a variable into
> these calculations?
I haven't sat down and worked through all the logic yet, but at least one
of two LDRs will be to obtain the value will be from an as yet uncached
location. Say we're running at 275MHz on a 50MHz bus. You're looking at
at least 275/50*8 (two cache lines will need to be read), = 44 cycles per
(currently it's only one or two cycles). If you have an application which
is sending over ethernet, say, then you're going to be hitting the data cache
hard, so this may be more like 88 cycles per. At 1MB/s, you're going to have
to do this 692 times, which means you've wasted 29064 cycles per second doing
a calculation above what it needs to be on a host.
However, you wouldn't want to cache the setting, since the base register is
free to be changed by any PNP BIOS or OS at any time. Only the host knows
what the current state of the PCI bus mapping is.
I do not expect to receive a reply which says "it's only 29064 cycles per
second", because if I do, I'll bounce all your "lets save a cycle here and
there" patches back at you! ;O
> Obviously in a particular implementation there might be issues like interrupts
> that prevent everything from working in quite the way you might hope, but not
> all the world is a PC.
Oh I wish that everyone else knew that. However, unless I am mistaken, this
thread was talking about an EBSA in a PC, which is after all how most people
are going to use it when in add-in mode. In order not to upset the host
configuration, everything to do with the handling of the PCI bus should be
done correctly, and definitely not how your patch does it.
> If you know that the kernel will be running as a host implementation, you can
> take some shortcuts like hardwiring the offsets in virt_to_bus, and having a
> configuration option for that is just fine. But I see no reason to consider
> the two modes as completely separate.
Maybe it doesn't have to be separate if it's done in the right way, but so far
I have not seen "the right way", despite pointing this flaw out in a previous
email. I have not seen that there is demand for a combined host and add-in
kernel to date either.
I think before even looking into/touching this area/allowing patches to
touch this area, I want to see the generic PCI code stabilise. Martin Mares
has some patches outstanding for it.
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