Dave Schneider writes:
> r0 is set to 517d on entry to aligned_call which is
> the setting for C1 of the mmu. Bits 6 and 14 look
> suspect to me but clearing them them in any
> combination has not effect.
0x517d is correct. The StrongARMs control register is updated
by a read-modify-write operation. The read is in proc-sa110.S
in the __sa110_setup function (which sets 0x113d). The 0x4000
comes from the page table CR (due to incomplete decoding of the
register number by the SA110), and the 0x0040 is "always set"
by the SA110.
Do you have any debug or any extra code around this area?
PS, does your mailer have to squish emails down to 54-character lines?
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