Thanks for your comments on the patch. Like I said, this patch was from a
snapshot of the system I'm debugging, and definitely not clean enough to
apply to the linux-arm tree. Most of the things you had comments about were
debugging code I inserted that I have now removed.
The code at the beginning that disables the I cache was there so the logic
analyzer can trace instruction execution. Too bad StrongARM didn't
implement the ARM debug mode. I would like to be able to run the kernel
with the I cache disabled for this reason.
In order to run with the I cache disabled, I would like to add the following
instructions to __create_page_tables:
+ /*
+ * map virtual addresses 0x00000000-0x00200000
+ * to physical addresses 0x00000000-0x00200000
+ * in case instructions after MMU is enabled are 'fetched
flat'
+ * e.g. if icache is disabled
+ */
+ mov r0, r4 @ r4 contains physaddr of
pagetable
+ mov r3, #0x0c @ SECT_CACHEABLE |
SECT_BUFFERABLE
+ orr r3, r3, r8 @ r8 contains page
table flags
+ add r3, r3, r5 @ r5 contains start
of DRAM
+ str r3, [r0], #4
+ add r3, r3, #1 << 20 @ next 1MB segment
address
+ str r3, [r0], #4
/*
* map in two sections (2MB) for kernel.
* these are marked cacheable and bufferable.
*/
add r0, r4, #(TEXTADDR - 0x8000) >> 18
mov r3, #0x0c @ SECT_CACHEABLE |
SECT_BUFFERABLE
orr r3, r3, r8
add r3, r3, r5
...
I don't quite fully understand the code that configures the kernel's MMU
table, but I'm assuming that these mappings will be overwritten at that
time. Is that correct?
Regarding your 2.3.34 patch: this code is now enabling the I cache before
enabling the MMU. Does this make two places where the I cache is enabled
(here and proc-sa110.S)? Would you accept a patch that conditionalizes this
with #ifdef CONFIG_NOICACHE?
Regarding the 'mcr p15, 0, r0, c1, c0' after __aligned_call. The SA110
manual does not specify when the MMU is enabled or when the PC is updated by
the following 'mov pc, lr'. I have seen the processor fetch instructions
from physical addresses 0xC00xxxxx following this mov, indicating that it is
at least prefetching the instructions following the mov before the MMU has
been enabled. I will recheck this now to see if that causes it to fail or
if it refetches down the correct path. If not, I would like to add three
mov's between the mcr and the 'mov pc, lr'. If you accept the above MMU
table modification, then you can drop the enabling of the I cache and its
three mov's from your 2.3.34 patch.
-Jamey
unsubscribe: body of `unsubscribe linux-arm' to [EMAIL PROTECTED]
++ Please use [EMAIL PROTECTED] for ++
++ kernel-related discussions. ++
