It really blew my mind when Tim Goetze <[EMAIL PROTECTED]> said:
> >> Assuming the clocks on the cards really *are* running at constant
> >> rates. I wonder how consistent those things are? (I'm not a (digital)
> >> hardware guy...)
> >
> >I was and I can tell you they will drift relative to one another. It
> >will probably be less than 50 part per million.
>
> i wonder why they don't just take the PCI clock and divide it to generate
> the sample word clock.
Two problems:
- Most of the A-D and D-A converter chips use delta-sigma technology which
requires an input clock at 128 times the word clock.
- Generating 128 times word clock for a number of different sample rate
frequencies (22k05, 32k, 44k1, 48k, etc) from the PCI clock of 33MHz
with low jitter would require a very difficult to design Phase Locked
Loop. I know because I designed one.
Erik
--
+-----------------------------------------------------------+
Erik de Castro Lopo [EMAIL PROTECTED] (Yes it's valid)
+-----------------------------------------------------------+
$_='while(read+STDIN,$_,2048){$a=29;$b=73;$c=142;$t=255;@t=map{$_%16or$t^=$c^=(
$m=(11,10,116,100,11,122,20,100)[$_/16%8])&110;$t^=(72,@z=(64,72,$a^=12*($_%16
-2?0:$m&17)),$b^=$_%64?12:0,@z)[$_%8]}(16..271);if((@a=unx"C*",$_)[20]&48){$h
=5;$_=unxb24,join"",@b=map{xB8,unxb8,chr($_^$a[--$h+84])}@ARGV;s/...$/1$&/;$
d=unxV,xb25,$_;$e=256|(ord$b[4])<<9|ord$b[3];$d=$d>>8^($f=$t&($d>>12^$d>>4^
$d^$d/8))<<17,$e=$e>>8^($t&($g=($q=$e>>14&7^$e)^$q*8^$q<<6))<<9,$_=$t[$_]^
(($h>>=8)+=$f+(~$g&$t))for@a[128..$#a]}print+x"C*",@a}';s/x/pack+/g;eval
