| From: Raj, Ashok <ashok....@intel.com> | Sent: Wednesday, September 27, 2017 12:07 PM | | looking at the debug output i got from Harsh it still looks like a bug in | the code. | | [ 538.284589] __domain_mapping nr_pages 0x1 | [ 538.284600] __domain_mapping sg_res 0x1 sg->dma_address 0xf291000e dma len | 0x38 pteval 0x3cbce3003 phys_pfn 0x3cbce3 | [ 538.284604] chelsio driver - offset 4110 len 56 dma addr f291000e dma len | 56 | [ 538.284667] DMAR: DRHD: handling fault status reg 2 | [ 538.290017] DMAR: [DMA Write] Request device [02:00.4] fault addr f2910000 | [fault reason 05] PTE Write access is not set | | somehow when crypto_authenc_encrypt() -> scatterwalk_ffwd()-> sg_set_page() | | ->sg_set_page(dst, sg_page(src), src->length - len, src->offset + len); | | src->offset + len gets set as sg->offset in sg_set_page(). Either the | assumption that there should be room is incorrect, or some higher order | crypto | code that ends up setting the offset did the wrong calculation. | | if src->offset is already towards the end of the page, then offset+len will | go beyond the end of page.
Hhmmm, it seems like we need Herbert to comment on this. Herbert, is there any specific debugging information that you'd like to see here? Casey
