Hi Albert,
On Wed, 16 Jan 2008, Albert Comerma wrote:
> Hi, I would like to build a driver for Pinacle 320CX card based on this
> chips combination, I already managed to get the card detected and firmware
> downloaded to dibcom chip.
> For dvb CX25843 is useless, so it can be skiped, but the problem is how to
> add XC3028 to the dibcom chip. I've got some basic cuestions;
>
> - Firmware... dvb usual dibcom firmware should work for this part? which
> XC3028 firmware should I use?
USB firmware for dib0700 is the normal one. For Xceive, the base-firmware
is the same as on other cards, for the standard-firmware I'm not sure, do
you have a list of firmware available?
> - Gpio's, what gpio's are suposed to be used between dibcom and XC3028?
It is GPIO 8 of the demod:
so
dib7000m_set_gpio(.., 8, 0, 0);
msleep(1);
dib7000m_set_gpio(.., 8, 0, 1);
in case of dib7000m - for dib7000p it is dib7000p_set_gpio
> - I2C; should be used as on other tunners, wich address uses XC3028?
0xc2 = 0x61.
> I'm having a look to the latest
> /v4l-dvb-7d364b375fb7/linux/drivers/media/video/tuner-xc2028* I hope those
> are the correct files for it...
I don't know this part. Mauro was working on it, don't know if it is
committed.
You will also need the stuff from the attachment.
Patrick.
--
Mail: [EMAIL PROTECTED]
WWW: http://www.wi-bw.tfh-wildau.de/~pboettch/
struct dibx000_agc_config xc3028_agc_config = {
BAND_VHF | BAND_UHF, // band_caps
/* P_agc_use_sd_mod1=0, P_agc_use_sd_mod2=0, P_agc_freq_pwm_div=0,
P_agc_inv_pwm1=0, P_agc_inv_pwm2=0,
* P_agc_inh_dc_rv_est=0, P_agc_time_est=3, P_agc_freeze=0,
P_agc_nb_est=2, P_agc_write=0 */
(0 << 15) | (0 << 14) | (0 << 11) | (0 << 10) | (0 << 9) | (0 << 8) |
(3 << 5) | (0 << 4) | (2 << 1) | (0 << 0), // setup
712, // inv_gain
21, // time_stabiliz
0, // alpha_level
118, // thlock
0, // wbd_inv
2867, // wbd_ref
0, // wbd_sel
2, // wbd_alpha
0, // agc1_max
0, // agc1_min
39718, // agc2_max
9930, // agc2_min
0, // agc1_pt1
0, // agc1_pt2
0, // agc1_pt3
0, // agc1_slope1
0, // agc1_slope2
0, // agc2_pt1
128, // agc2_pt2
29, // agc2_slope1
29, // agc2_slope2
17, // alpha_mant
27, // alpha_exp
23, // beta_mant
51, // beta_exp
1, // perform_agc_softsplit
};
/* PLL Configuration for COFDM BW_MHz = 8.000000 With external clock =
30.000000 */
struct dibx000_bandwidth_config xc3028_bw_config = {
60000, 30000, // internal, sampling
1, 8, 3, 1, 0, // pll_cfg: prediv, ratio, range, reset, bypass
0, 0, 1, 1, 0, // misc: refdiv, bypclk_div, IO_CLK_en_core, ADClkSrc,
modulo
(3 << 14) | (1 << 12) | (524 << 0), // sad_cfg: refsel, sel, freq_15k
(1 << 25) | 5816102, // ifreq = 5.200000 MHz
20452225, // timf
30000000, // xtal_hz
};
struct dibx000_bandwidth_config xc3028_bw_config_12mhz = {
60000, 30000, // internal, sampling
1, 20, 3, 1, 0, // pll_cfg: prediv, ratio, range, reset, bypass
0, 0, 1, 1, 0, // misc: refdiv, bypclk_div, IO_CLK_en_core, ADClkSrc,
modulo
(3 << 14) | (1 << 12) | (524 << 0), // sad_cfg: refsel, sel, freq_15k
(1 << 25) | 5816102, // ifreq = 5.200000 MHz
20452225, // timf
};
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