From: Chew, Chiau Ee <chiau.ee.c...@intel.com>
These two patches contains the additional changes required for BayTrail LPSS
I2C on top of the patch that Mika Westerberg has submitted previously which
is still in the pending queue:
"[PATCH v2] i2c: designware-pci: Add Baytrail PCI IDs"
http://www.spinics.net/lists/linux-i2c/msg14709.html
Basically, the changes inclusive of:
i. enable the pci glue layer to pass in target HCNT, LCNT
and SDA hold time values to core layer if they are known
beforehand, eg: for BayTrail.
ii. declare the BayTrail LPSS I2C controllers are capable of
supporting 10-bit addressing mode functionality.
Chew, Chiau Ee (2):
i2c: designware-pci: add 10-bit addressing mode functionality for BYT
I2C
i2c: designware-pci: set ideal HCNT, LCNT and SDA hold time value
drivers/i2c/busses/i2c-designware-pcidrv.c | 51 ++++++++++++++++++++++++---
1 files changed, 45 insertions(+), 6 deletions(-)
--
1.7.4.4
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