On Wed, 6 Dec 2006, Russell King wrote: > On Wed, Dec 06, 2006 at 10:56:14AM -0800, Christoph Lameter wrote: > > I'd really appreciate a cmpxchg that is generically available for > > all arches. It will allow lockless implementation for various performance > > criticial portions of the kernel. > > Let's recap on cmpxchg. > > For CPUs with no atomic operation other than SWP, it is not lockless.
But then its also just requires disable/enable interrupts on UP which may be cheaper than an atomic operation. > For CPUs with load locked + store conditional, it is expensive. Because it locks the bus? I am not that familiar with those architectures but it seems that those will have a general problem anyways. > If you want an operation for performance critical portions of the > kernel, please allow architecture maintainers the freedom to use their > best performance enhancements. And thereby denying the kernel developers to use a simple atomic SMP operation? Adding additional defines for each arch and each performance critical piece of kernel logic? - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
