Am Mittwoch, 9. März 2016, 10:37:03 schrieb Xing Zheng: > Thers are only two parent PLLs that APLL and GPLL for core on the > previous SoCs (RK3066/RK3188/RK3288/RK3368). Hence, we set fixed > GPLL as alternate parent when core is switching freq. > > Since RK3399 big.LITTLE architecture, we need to select and adapt > more PLLs (ALPLL/ABPLL/DPLL/GPLL) sources. > > Signed-off-by: Xing Zheng <[email protected]>
applied to my clk-branch for v4.7, with an adapted subject of "clk: rockchip: allow varying mux parameters for cpuclk pll-sources" Thanks Heiko
