tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
master
head: 6b5f04b6cf8ebab9a65d9c0026c650bb2538fd0f
commit: cc78eb22885bba64445cde438ba098de0104920f drm/radeon: properly byte swap
vce firmware setup
date: 8 weeks ago
reproduce:
# apt-get install sparse
git checkout cc78eb22885bba64445cde438ba098de0104920f
make ARCH=x86_64 allmodconfig
make C=1 CF=-D__CHECK_ENDIAN__
sparse warnings: (new ones prefixed by >>)
>> drivers/gpu/drm/radeon/vce_v1_0.c:181:25: sparse: cast to restricted __le32
drivers/gpu/drm/radeon/vce_v1_0.c:182:21: sparse: cast to restricted __le32
drivers/gpu/drm/radeon/vce_v1_0.c:186:18: sparse: cast to restricted __le32
drivers/gpu/drm/radeon/vce_v1_0.c:194:19: sparse: cast to restricted __le32
>> drivers/gpu/drm/radeon/vce_v1_0.c:194:17: sparse: incorrect type in
>> assignment (different base types)
drivers/gpu/drm/radeon/vce_v1_0.c:194:17: expected unsigned int
[unsigned] [usertype] <noident>
drivers/gpu/drm/radeon/vce_v1_0.c:194:17: got restricted __le32
[usertype] <noident>
drivers/gpu/drm/radeon/vce_v1_0.c:199:17: sparse: cast to restricted __le32
drivers/gpu/drm/radeon/vce_v1_0.c:205:31: sparse: cast to restricted __le32
vim +181 drivers/gpu/drm/radeon/vce_v1_0.c
96 if (ring->idx == TN_RING_TYPE_VCE1_INDEX)
97 WREG32(VCE_RB_WPTR, ring->wptr);
98 else
99 WREG32(VCE_RB_WPTR2, ring->wptr);
100 }
101
> 102 void vce_v1_0_enable_mgcg(struct radeon_device *rdev, bool enable)
103 {
104 u32 tmp;
105
106 if (enable && (rdev->cg_flags & RADEON_CG_SUPPORT_VCE_MGCG)) {
107 tmp = RREG32(VCE_CLOCK_GATING_A);
108 tmp |= CGC_DYN_CLOCK_MODE;
109 WREG32(VCE_CLOCK_GATING_A, tmp);
110
111 tmp = RREG32(VCE_UENC_CLOCK_GATING);
112 tmp &= ~0x1ff000;
113 tmp |= 0xff800000;
114 WREG32(VCE_UENC_CLOCK_GATING, tmp);
115
116 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
117 tmp &= ~0x3ff;
118 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
119 } else {
120 tmp = RREG32(VCE_CLOCK_GATING_A);
121 tmp &= ~CGC_DYN_CLOCK_MODE;
122 WREG32(VCE_CLOCK_GATING_A, tmp);
123
124 tmp = RREG32(VCE_UENC_CLOCK_GATING);
125 tmp |= 0x1ff000;
126 tmp &= ~0xff800000;
127 WREG32(VCE_UENC_CLOCK_GATING, tmp);
128
129 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
130 tmp |= 0x3ff;
131 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
132 }
133 }
134
135 static void vce_v1_0_init_cg(struct radeon_device *rdev)
136 {
137 u32 tmp;
138
139 tmp = RREG32(VCE_CLOCK_GATING_A);
140 tmp |= CGC_DYN_CLOCK_MODE;
141 WREG32(VCE_CLOCK_GATING_A, tmp);
142
143 tmp = RREG32(VCE_CLOCK_GATING_B);
144 tmp |= 0x1e;
145 tmp &= ~0xe100e1;
146 WREG32(VCE_CLOCK_GATING_B, tmp);
147
148 tmp = RREG32(VCE_UENC_CLOCK_GATING);
149 tmp &= ~0xff9ff000;
150 WREG32(VCE_UENC_CLOCK_GATING, tmp);
151
152 tmp = RREG32(VCE_UENC_REG_CLOCK_GATING);
153 tmp &= ~0x3ff;
154 WREG32(VCE_UENC_REG_CLOCK_GATING, tmp);
155 }
156
157 int vce_v1_0_load_fw(struct radeon_device *rdev, uint32_t *data)
158 {
159 struct vce_v1_0_fw_signature *sign = (void*)rdev->vce_fw->data;
160 uint32_t chip_id;
161 int i;
162
163 switch (rdev->family) {
164 case CHIP_TAHITI:
165 chip_id = 0x01000014;
166 break;
167 case CHIP_VERDE:
168 chip_id = 0x01000015;
169 break;
170 case CHIP_PITCAIRN:
171 case CHIP_OLAND:
172 chip_id = 0x01000016;
173 break;
174 case CHIP_ARUBA:
175 chip_id = 0x01000017;
176 break;
177 default:
178 return -EINVAL;
179 }
180
> 181 for (i = 0; i < le32_to_cpu(sign->num); ++i) {
182 if (le32_to_cpu(sign->val[i].chip_id) == chip_id)
183 break;
184 }
185
186 if (i == le32_to_cpu(sign->num))
187 return -EINVAL;
188
189 data += (256 - 64) / 4;
190 data[0] = sign->val[i].nonce[0];
191 data[1] = sign->val[i].nonce[1];
192 data[2] = sign->val[i].nonce[2];
193 data[3] = sign->val[i].nonce[3];
> 194 data[4] = cpu_to_le32(le32_to_cpu(sign->len) + 64);
195
196 memset(&data[5], 0, 44);
197 memcpy(&data[16], &sign[1], rdev->vce_fw->size - sizeof(*sign));
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