On Mar 28, 2016, at 4:56 PM, Guenter Roeck <li...@roeck-us.net> wrote: > >> So taken from the timer offset 0x0208A000 I just have a generic counter >> register CPU0_APCS_GPT0_CNT at 0x8 >> >> What doc are you looking at? >> > "Qualcomm Snapdragon 600 Processor APQ8064 Hardware Register Description" > > It is available for download from the Qualcomm web site. > > See chapter 12.10.3, "Watchdog timer registers". The register block is at > 0x28882000. Registers are almost the same, except for the offset and the > definition of the bits in the enable register. > > LPASS is "Low Power Audio Subsystem". Maybe it has its own watchdog.
This block is here: 11.15 KPSS CPU0 Timer Registers (0x0208A000 CPU0_APCS_TMR_BASE) -M
