On 04/20/2016 07:30 AM, Laxman Dewangan wrote:
NVIDIA's Tegra210 support the HW debounce in the GPIO
controller for all its GPIO pins.
Add support for setting debounce timing by implementing the
set_debounce callback of gpiochip.
diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c
+static int tegra_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset,
+ /* There is only one debounce count register per port and hence
+ * set the maximum of current and requested debounce time.
+ */
+ if (tgi->bank_info[bank].dbc_cnt[port] < debounce_ms) {
+ tegra_gpio_writel(tgi, debounce_ms, GPIO_DBC_CNT(tgi, offset));
+ tgi->bank_info[bank].dbc_cnt[port] = debounce_ms;
+ }
Do we need any locking there? I imagine the GPIO core doesn't prevent
different threads/drivers from manipulating different GPIOs in parallel
on different cores.
