On Mon, May 23, 2016 at 08:48:41PM +0530, Shreyas B. Prabhu wrote: > POWER ISA v3 defines a new idle processor core mechanism. In summary, > a) new instruction named stop is added. > b) new per thread SPR named PSSCR is added which controls the behavior > of stop instruction. > > Supported idle states and value to be written to PSSCR register to enter > any idle state is exposed via ibm,cpu-idle-state-names and > ibm,cpu-idle-state-psscr respectively. To enter an idle state, > platform provided power_stop() needs to be invoked with the appropriate > PSSCR value. > > This patch adds support for this new mechanism in cpuidle powernv driver. > > Cc: Rafael J. Wysocki <[email protected]> > Cc: Daniel Lezcano <[email protected]> > Cc: [email protected] > Cc: Michael Ellerman <[email protected]> > Cc: Paul Mackerras <[email protected]> > Cc: [email protected] > Signed-off-by: Shreyas B. Prabhu <[email protected]>
Reviewed-by: Gautham R. Shenoy <[email protected]> -- Thanks and Regards gautham.
