The patch: perf/x86/intel: Protect LBR and extra_regs against KVM lying introduced an extra test for LBR support but did not move the dmesg accordingly. This problem is fixed in first patch in this series.
When a machine that used LBR is rebooted using kexec, the extra test for LBR support may fail due to a hw bug/quirk in Haswell that generate a #GPF when restoring the value of MSR_LAST_BRANCH_FROM_* msrs with sign-extended valuse (e.p. kernel addresses). During normal execution, this problem is masked by a work-around to another hw bug that prevented FREEZE_LBRS_ON_PMI from be used in kernel branches, introduced in "perf/x86/intel: Add Haswell LBR call stack support". The second patch in this series contains a workaround for the MSR_LAST_BRANCH_FROM_* hw bug/quirk. The last patch is not to be commited, but to test the second patch. It removes the effect of the FREEZE_LBRS_ON_PMI work-around by allowing LBR call-stack for kernel addresses. This series is rebased at torvalds/linux/master . David Carrillo-Cisneros (3): perf/x86/intel: output LBR support statement after validation perf/x86/intel: fix for MSR_LAST_BRANCH_FROM_x quirk when no TSX perf, perf/tool: trigger lbr_from signext bug arch/x86/events/intel/core.c | 20 +++++++++++ arch/x86/events/intel/lbr.c | 83 +++++++++++++++++++++++++++++++++++++------- arch/x86/events/perf_event.h | 2 ++ tools/perf/util/evsel.c | 17 +++++++-- 4 files changed, 106 insertions(+), 16 deletions(-) -- 2.8.0.rc3.226.g39d4020
