Commit-ID:  9485f8b6a75921e1b9e94b001cdb45872a598534
Gitweb:     http://git.kernel.org/tip/9485f8b6a75921e1b9e94b001cdb45872a598534
Author:     Andy Shevchenko <[email protected]>
AuthorDate: Mon, 13 Jun 2016 21:28:01 +0300
Committer:  Ingo Molnar <[email protected]>
CommitDate: Tue, 14 Jun 2016 12:44:51 +0200

x86/platform/atom/punit: Enable support for Merrifield

Intel Merrifield platform has Punit generation that somehow compatible to what
is already supported by punit_atom_debug driver.

Add necessary bits to enable that support.

Signed-off-by: Andy Shevchenko <[email protected]>
Acked-by: Thomas Gleixner <[email protected]>
Cc: Bjorn Helgaas <[email protected]>
Cc: Linus Torvalds <[email protected]>
Cc: Peter Zijlstra <[email protected]>
Link: 
http://lkml.kernel.org/r/1465842481-136852-2-git-send-email-andriy.shevche...@linux.intel.com
Signed-off-by: Ingo Molnar <[email protected]>
---
 arch/x86/platform/atom/punit_atom_debug.c | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/arch/x86/platform/atom/punit_atom_debug.c 
b/arch/x86/platform/atom/punit_atom_debug.c
index 1097829..8ff7b93 100644
--- a/arch/x86/platform/atom/punit_atom_debug.c
+++ b/arch/x86/platform/atom/punit_atom_debug.c
@@ -26,8 +26,6 @@
 #include <asm/intel-family.h>
 #include <asm/iosf_mbi.h>
 
-/* Power gate status reg */
-#define PWRGT_STATUS           0x61
 /* Subsystem config/status Video processor */
 #define VED_SS_PM0             0x32
 /* Subsystem config/status ISP (Image Signal Processor) */
@@ -36,12 +34,16 @@
 #define MIO_SS_PM              0x3B
 /* Shift bits for getting status for video, isp and i/o */
 #define SSS_SHIFT              24
+
+/* Power gate status reg */
+#define PWRGT_STATUS           0x61
 /* Shift bits for getting status for graphics rendering */
 #define RENDER_POS             0
 /* Shift bits for getting status for media control */
 #define MEDIA_POS              2
 /* Shift bits for getting status for Valley View/Baytrail display */
 #define VLV_DISPLAY_POS                6
+
 /* Subsystem config/status display for Cherry Trail SOC */
 #define CHT_DSP_SSS            0x36
 /* Shift bits for getting status for display */
@@ -53,6 +55,14 @@ struct punit_device {
        int sss_pos;
 };
 
+static const struct punit_device punit_device_tng[] = {
+       { "DISPLAY",    CHT_DSP_SSS,    SSS_SHIFT },
+       { "VED",        VED_SS_PM0,     SSS_SHIFT },
+       { "ISP",        ISP_SS_PM0,     SSS_SHIFT },
+       { "MIO",        MIO_SS_PM,      SSS_SHIFT },
+       { NULL }
+};
+
 static const struct punit_device punit_device_byt[] = {
        { "GFX RENDER", PWRGT_STATUS,   RENDER_POS },
        { "GFX MEDIA",  PWRGT_STATUS,   MEDIA_POS },
@@ -145,6 +155,7 @@ static void punit_dbgfs_unregister(void)
 
 static const struct x86_cpu_id intel_punit_cpu_ids[] = {
        ICPU(INTEL_FAM6_ATOM_SILVERMONT1, punit_device_byt),
+       ICPU(INTEL_FAM6_ATOM_MERRIFIELD1, punit_device_tng),
        ICPU(INTEL_FAM6_ATOM_AIRMONT,     punit_device_cht),
        {}
 };

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