On Mon, 11 Jul 2016 21:31:04 +0200 Ingo Molnar <[email protected]> wrote:
> > * Jacob Pan <[email protected]> wrote: > > > On Mon, 11 Jul 2016 07:59:19 -0700 > > "Chen, Yu C" <[email protected]> wrote: > > > > > Currently it is in your x86/timer tree: > > > > > > commit fc273eeef314cdaf0ac992b400d126f8184a4d1c > > > Author: Len Brown <[email protected]> > > > Date: Fri Jun 17 01:22:49 2016 -0400 > > > > > > x86/tsc_msr: Extend to include Intel Core Architecture > > > > > > > > > Previously we found this patch might decrease the performance on > > > one of our servers, due to the small gap between using old PIT > > > calibration and new MSR calibration method, so we currently would > > > like to hold this patch for now, until we got a clear answer from > > > our architect. Would you please help revert this patch (the other > > > patches are safe and can be merged), sorry for the inconvenience. > > > > > I modified the subject slightly to be more specific. > > Adding lkml and x86 list, and a few more people. > > This commit is also affected, won't compile if we revert the one > > above. > > > > 37c528e... x86/tsc_msr: Fix rdmsr(MSR_PLATFORM_INFO) unsafe warning > > in KVM guest > > Ok, I've rebased tip:x86/timers, it now includes the following > commits: > > ff4c86635ee1 x86/tsc: Enumerate BXT tsc_khz via CPUID > aa297292d708 x86/tsc: Enumerate SKL cpu_khz and tsc_khz via CPUID > 02c0cd2dcf7f x86/tsc_msr: Remove irqoff around MSR-based TSC > enumeration 6fcb41cdaee5 x86/tsc_msr: Add Airmont reference clock > values 05680e7fa8a4 x86/tsc_msr: Correct Silvermont reference clock > values 9e0cae9f6227 x86/tsc_msr: Update comments, expand definitions > 14bb4e34860a x86/tsc_msr: Remove debugging messages > ba8268330dc1 x86/tsc_msr: Identify Intel-specific code > fc5f3ac24720 Revert "x86/tsc: Add missing Cherrytrail frequency to > the table" > > Does that work for you? > works for me but Yu has to confirm. > Thanks, > > Ingo
