Hi,
On Tuesday, July 12, 2016 12:16:19 PM Colin King wrote:
> From: Colin Ian King <colin.k...@canonical.com>
>
> According to the HPT366 data sheet, PCI config space dword 0x40-0x43
> bits 11:8 specify the primary drive cmd_high_time, however,
> currently just 3 bits of the 4 are being used because the mask
> is 0x700 and not 0x0f00. Fix the mask, allowing for the 40MHz clock
> to be detected.
>
> Signed-off-by: Colin Ian King <colin.k...@canonical.com>
Acked-by: Bartlomiej Zolnierkiewicz <b.zolnier...@samsung.com>
Thanks for the patch, could you also fix also the old driver
(drivers/ide/hpt366.c)?
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics
> ---
> drivers/ata/pata_hpt366.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/ata/pata_hpt366.c b/drivers/ata/pata_hpt366.c
> index e5fb752..a219a50 100644
> --- a/drivers/ata/pata_hpt366.c
> +++ b/drivers/ata/pata_hpt366.c
> @@ -368,7 +368,7 @@ static int hpt36x_init_one(struct pci_dev *dev, const
> struct pci_device_id *id)
>
> /* PCI clocking determines the ATA timing values to use */
> /* info_hpt366 is safe against re-entry so we can scribble on it */
> - switch ((reg1 & 0x700) >> 8) {
> + switch ((reg1 & 0xf00) >> 8) {
> case 9:
> hpriv = &hpt366_40;
> break;
