Add TPM2.0 PTP FIFO compatible SPI interface for chips with Cr50
firmware. Several timing-related properties that may differ from
one firmware version to another are added to devicetree.
Document these properties.
Signed-off-by: Andrey Pronin <apro...@chromium.org>
---
.../devicetree/bindings/security/tpm/cr50_spi.txt | 32 ++++++++++++++++++++++
1 file changed, 32 insertions(+)
create mode 100644 Documentation/devicetree/bindings/security/tpm/cr50_spi.txt
diff --git a/Documentation/devicetree/bindings/security/tpm/cr50_spi.txt
b/Documentation/devicetree/bindings/security/tpm/cr50_spi.txt
new file mode 100644
index 0000000..f212b6b
--- /dev/null
+++ b/Documentation/devicetree/bindings/security/tpm/cr50_spi.txt
@@ -0,0 +1,32 @@
+* H1 Secure Microcontroller with Cr50 Firmware on SPI Bus.
+
+H1 Secure Microcontroller running Cr50 firmware provides several
+functions, including TPM-like functionality. It communicates over
+SPI using the FIFO protocol described in the PTP Spec, section 6.
+
+Required properties:
+- compatible: Should be "google,cr50".
+- spi-max-frequency: Maximum SPI frequency.
+
+Optional properties:
+- access-delay-ms: Required delay between subsequent transactions on SPI.
+- sleep-delay-ms: Time after the last SPI activity, after which the chip
+ may go to sleep.
+- wake-start-delay-ms: Time after initiating wake up before the chip is
+ ready to accept commands over SPI.
+
+Example:
+
+&spi0 {
+ status = "okay";
+
+ cr50@0 {
+ compatible = "google,cr50";
+ reg = <0>;
+ spi-max-frequency = <800000>;
+
+ access-delay-ms = <2>;
+ sleep-delay-ms = <1000>;
+ wake-start-delay-ms = <60>;
+ };
+};
--
2.6.6
