On Tue, Jul 19, 2016 at 01:40:41PM +0100, Juri Lelli wrote: > ARM systems may be configured to have cpus with different power/performance > characteristics within the same chip. In this case, additional information > has to be made available to the kernel (the scheduler in particular) for it > to be aware of such differences and take decisions accordingly. > > Therefore, this patch aims at standardizing cpu capacities device tree > bindings for ARM platforms. Bindings define cpu capacity-dmips-mhz > parameter, to allow operating systems to retrieve such information from > the device tree and initialize related kernel structures, paving the way > for common code in the kernel to deal with heterogeneity. > > Cc: Rob Herring <robh...@kernel.org> > Cc: Pawel Moll <pawel.m...@arm.com> > Cc: Mark Rutland <mark.rutl...@arm.com> > Cc: Ian Campbell <ijc+devicet...@hellion.org.uk> > Cc: Kumar Gala <ga...@codeaurora.org> > Cc: Maxime Ripard <maxime.rip...@free-electrons.com> > Cc: Olof Johansson <o...@lixom.net> > Cc: Gregory CLEMENT <gregory.clem...@free-electrons.com> > Cc: Paul Walmsley <p...@pwsan.com> > Cc: Linus Walleij <linus.wall...@linaro.org> > Cc: Chen-Yu Tsai <w...@csie.org> > Cc: Thomas Petazzoni <thomas.petazz...@free-electrons.com> > Cc: devicet...@vger.kernel.org > Signed-off-by: Juri Lelli <juri.le...@arm.com> > --- > > Changes from v1: > - removed section regarding capacity-scale > - added information regarding normalization > > Changes from v4: > - binding changed to capacity-dmips-mhz > - sections and changelod updated accordingly > > Changes from v5: > - addressed Mark and Vincent comments > --- > .../devicetree/bindings/arm/cpu-capacity.txt | 236 > +++++++++++++++++++++ > Documentation/devicetree/bindings/arm/cpus.txt | 10 + > 2 files changed, 246 insertions(+) > create mode 100644 Documentation/devicetree/bindings/arm/cpu-capacity.txt
I guess I'm okay with the scaled values, so: Acked-by: Rob Herring <r...@kernel.org> [...] > +Example 2 (ARM 32-bit, 4-cpu system, two clusters, > + cpus 0,1@1GHz, cpus 2,3@500MHz): > +capacities-dmips-mhz are scaled w.r.t. 2 (cpu@0 and cpu@1), this means that > first > +cpu@0 and cpu@1 are twice fast than cpu@2 and cpu@3 (at the same frequency) This example is a bit confusing with both the capacity and frequency being half. I also find it a bit unrealistic to have a 2x performance difference on the same micro arch. But it is all just an example... Rob
