On Thursday 08 September 2016 10:04:55, Meng Yi wrote:
> If the FTM counter reaches the FTM_MOD value between the reading of the
> TOF bit and the writing of 0 to the TOF bit, the process of clearing the
> TOF bit does not work as expected when FTMx_CONF[NUMTOF] != 0 and the
> current TOF count is less than FTMx_CONF[NUMTOF]. If the above condition
> is met, the TOF bit remains set. If the TOF interrupt is enabled
> (FTMx_SC[TOIE] = 1), the TOF interrupt also remains asserted.
>
> Above is the errata discription
>
> The workaround is clearing TOF bit until it is cleaned(FTM counter doesn't
> always reache the FTM_MOD anyway),which may cost some cycles.
>
> Signed-off-by: Meng Yi <meng...@nxp.com>
> ---
> drivers/clocksource/fsl_ftm_timer.c | 9 ++++-----
> 1 file changed, 4 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/clocksource/fsl_ftm_timer.c
> b/drivers/clocksource/fsl_ftm_timer.c index 738515b..ade26e5 100644
> --- a/drivers/clocksource/fsl_ftm_timer.c
> +++ b/drivers/clocksource/fsl_ftm_timer.c
> @@ -83,11 +83,10 @@ static inline void ftm_counter_disable(void __iomem
> *base)
>
> static inline void ftm_irq_acknowledge(void __iomem *base)
> {
> - u32 val;
> -
> - val = ftm_readl(base + FTM_SC);
> - val &= ~FTM_SC_TOF;
> - ftm_writel(val, base + FTM_SC);
> + /*read and clean the FTM_SC_TOF bit until its cleared*/
> + while (FTM_SC_TOF & ftm_readl(base + FTM_SC))
> + ftm_writel(ftm_readl(base + FTM_SC) & (~FTM_SC_TOF),
> + base + FTM_SC);
> }
So you are essentially polling hardware in interrupt context. Please add a
sensible timeout to abort this loop in case of defective hardware, and maybe
disable the interrupt in that case.
Best regards,
Alexander
