On Thu, 8 Sep 2016, Fenghua Yu wrote:
> +extern struct static_key rdt_enable_key;
> +void __intel_rdt_sched_in(void *dummy);
> +
> struct clos_cbm_table {
> unsigned long cbm;
> unsigned int clos_refcnt;
> };
>
> +/*
> + * intel_rdt_sched_in() - Writes the task's CLOSid to IA32_PQR_MSR
> + *
> + * Following considerations are made so that this has minimal impact
> + * on scheduler hot path:
> + * - This will stay as no-op unless we are running on an Intel SKU
> + * which supports L3 cache allocation.
> + * - When support is present and enabled, does not do any
> + * IA32_PQR_MSR writes until the user starts really using the feature
> + * ie creates a rdtgroup directory and assigns a cache_mask thats
> + * different from the root rdtgroup's cache_mask.
> + * - Caches the per cpu CLOSid values and does the MSR write only
> + * when a task with a different CLOSid is scheduled in. That
> + * means the task belongs to a different rdtgroup.
> + * - Closids are allocated so that different rdtgroup directories
> + * with same cache_mask gets the same CLOSid. This minimizes CLOSids
> + * used and reduces MSR write frequency.
> + */
> +static inline void intel_rdt_sched_in(void)
> +{
> + /*
> + * Call the schedule in code only when RDT is enabled.
> + */
> + if (static_key_false(&rdt_enable_key))
static_branch_[un]likely() is the proper function to use.
> + __intel_rdt_sched_in(NULL);
> +
> +void __intel_rdt_sched_in(void *dummy)
What's the purpose of this dummy argument?
> +{
> + struct intel_pqr_state *state = this_cpu_ptr(&pqr_state);
> +
> + /*
> + * Currently closid is always 0. When user interface is added,
> + * closid will come from user interface.
> + */
> + if (state->closid == 0)
> + return;
> +
> + wrmsr(MSR_IA32_PQR_ASSOC, state->rmid, 0);
> + state->closid = 0;
> +}
Thanks,
tglx
