On Mon, 2016-10-17 at 09:55 +0200, Thomas Gleixner wrote: > On Sun, 16 Oct 2016, Borislav Petkov wrote: > > > > > > > > The spec can be found in Intel Software Developer Manual or in > > > Instruction Set Extensions Programming Reference. See > > > https://software.intel.com/sites/default/files/managed/69/78/3194 > > > 33-025.pdf. > > > > > > > > +/* Intel-defined CPU features, CPUID level 0x00000007:0 (edx), > > > word 18 */ > > > +#define X86_FEATURE_AVX512_4VNNIW (18*32+2) /* AVX-512 Neural > > > Network Instructions */ > > > +#define X86_FEATURE_AVX512_4FMAPS (18*32+3) /* AVX-512 Multiply > > > Accumulation Single precision */ > > > > This is getting ridiculous: we keep adding new leafs to > > ->x86_capability, thus bloating cpuinfo_x86 but then it is not even > > worth it - this patch defines only two bits. > > What's worse is that the Instruction Set Extensions Programming > Reference > manual says: > > CPUID.(EAX=07H, ECX=0):EDX[bit 02] AVX512_4FMAPS > CPUID.(EAX=07H, ECX=0):EBX[bit 03] AVX512_4VNNIW > > So AVX512_4VNNIW is in EBX not EDX. What's correct here? The manual > or the patch? > > I'm going to zap it. > The manual contains the typo in table 2.1 on page 2.2. Please compare it to the detailed description of CPUID in table 4.8 on page 2-16. There manual groups both new bits under EDX:
EDX Bits 01 - 00: Reserved Bit 02: AVX512_4VNNIW (Vector instructions for deep learning enhanced word variable precision.) Bit 03: AVX512_4FMAPS (Vector instructions for deep learning floating-point single precision.) Bits 31-04: Reserved The typo was acknowledged and is going to be fixed in next version of the document. Regards, Piotr
