Commit-ID: a2ce092be34c4951e23104a0bfdec08f9577fada Gitweb: http://git.kernel.org/tip/a2ce092be34c4951e23104a0bfdec08f9577fada Author: Rich Felker <dal...@libc.org> AuthorDate: Thu, 13 Oct 2016 21:51:06 +0000 Committer: Thomas Gleixner <t...@linutronix.de> CommitDate: Thu, 20 Oct 2016 20:10:17 +0200
of: Add J-Core timer bindings Signed-off-by: Rich Felker <dal...@libc.org> Acked-by: Rob Herring <r...@kernel.org> Cc: Mark Rutland <mark.rutl...@arm.com> Cc: devicet...@vger.kernel.org Cc: linux...@vger.kernel.org Cc: Daniel Lezcano <daniel.lezc...@linaro.org> Cc: Rob Herring <robh...@kernel.org> Link: http://lkml.kernel.org/r/8b107c292ed8cf8eed0fa283071fc8a930098628.1476393790.git.dal...@libc.org Signed-off-by: Thomas Gleixner <t...@linutronix.de> --- .../devicetree/bindings/timer/jcore,pit.txt | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/Documentation/devicetree/bindings/timer/jcore,pit.txt b/Documentation/devicetree/bindings/timer/jcore,pit.txt new file mode 100644 index 0000000..af5dd35 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/jcore,pit.txt @@ -0,0 +1,24 @@ +J-Core Programmable Interval Timer and Clocksource + +Required properties: + +- compatible: Must be "jcore,pit". + +- reg: Memory region(s) for timer/clocksource registers. For SMP, + there should be one region per cpu, indexed by the sequential, + zero-based hardware cpu number. + +- interrupts: An interrupt to assign for the timer. The actual pit + core is integrated with the aic and allows the timer interrupt + assignment to be programmed by software, but this property is + required in order to reserve an interrupt number that doesn't + conflict with other devices. + + +Example: + +timer@200 { + compatible = "jcore,pit"; + reg = < 0x200 0x30 0x500 0x30 >; + interrupts = < 0x48 >; +};
