Subject: [PATCH v5 04/18] x86/intel_rdt: Feature discovery
Subject should start with a verb. I.e.,
"x86/cpufeature: Add RDT CPUID feature bits"
On Sat, Oct 22, 2016 at 06:19:51AM -0700, Fenghua Yu wrote:
> From: Fenghua Yu <fenghua...@intel.com>
>
> Check CPUID leaves for all the Resource Director Technology (RDT)
> Cache Allocation Technology (CAT) bits.
>
> Presence of allocation features:
> CPUID.(EAX=7H, ECX=0):EBX[bit 15] X86_FEATURE_RDT_A
>
> L2 and L3 caches are each separately enabled:
> CPUID.(EAX=10H, ECX=0):EBX[bit 1] X86_FEATURE_CAT_L3
> CPUID.(EAX=10H, ECX=0):EBX[bit 2] X86_FEATURE_CAT_L2
>
> L3 cache may support independent control of allocation for
> code and data (CDP = Code/Data Prioritization):
> CPUID.(EAX=10H, ECX=1):ECX[bit 2] X86_FEATURE_CDP_L3
>
> Signed-off-by: Fenghua Yu <fenghua...@intel.com>
> ---
> arch/x86/include/asm/cpufeatures.h | 5 +++++
> arch/x86/kernel/cpu/scattered.c | 3 +++
> 2 files changed, 8 insertions(+)
>
> diff --git a/arch/x86/include/asm/cpufeatures.h
> b/arch/x86/include/asm/cpufeatures.h
> index 1188bc8..21f4a7e 100644
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@ -195,6 +195,10 @@
>
> #define X86_FEATURE_INTEL_PT ( 7*32+15) /* Intel Processor Trace */
>
No newlines when consective bits.
> +#define X86_FEATURE_CAT_L3 ( 7*32+16) /* Cache Allocation Technology L3 */
> +#define X86_FEATURE_CAT_L2 ( 7*32+17) /* Cache Allocation Technology L2 */
> +#define X86_FEATURE_CDP_L3 ( 7*32+18) /* Code and Data Prioritization L3 */
Also, this patch or even better, the whole patchset needs to be at least
test-merged with tip/master to check for conflicting changes. Like this
one here:
#define X86_FEATURE_INTEL_PT ( 7*32+15) /* Intel Processor Trace */
#define X86_FEATURE_AVX512_4VNNIW (7*32+16) /* AVX-512 Neural Network
Instructions */
^^^^^^^
#define X86_FEATURE_AVX512_4FMAPS (7*32+17) /* AVX-512 Multiply Accumulation
Single precision */
^^^^^^
#define X86_FEATURE_CAT_L3 ( 7*32+16) /* Cache Allocation Technology L3 */
^^^^^^^
#define X86_FEATURE_CAT_L2 ( 7*32+17) /* Cache Allocation Technology L2 */
^^^^^^^
#define X86_FEATURE_CDP_L3 ( 7*32+18) /* Code and Data Prioritization L3 */
> /* Virtualization flags: Linux defined, word 8 */
> #define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */
> #define X86_FEATURE_VNMI ( 8*32+ 1) /* Intel Virtual NMI */
> @@ -219,6 +223,7 @@
> #define X86_FEATURE_RTM ( 9*32+11) /* Restricted Transactional
> Memory */
> #define X86_FEATURE_CQM ( 9*32+12) /* Cache QoS Monitoring */
> #define X86_FEATURE_MPX ( 9*32+14) /* Memory Protection
> Extension */
> +#define X86_FEATURE_RDT_A ( 9*32+15) /* Resource Director Technology
> Allocation */
> #define X86_FEATURE_AVX512F ( 9*32+16) /* AVX-512 Foundation */
> #define X86_FEATURE_AVX512DQ ( 9*32+17) /* AVX-512 DQ (Double/Quad granular)
> Instructions */
> #define X86_FEATURE_RDSEED ( 9*32+18) /* The RDSEED instruction */
> diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c
> index 8cb57df..11f39a2 100644
> --- a/arch/x86/kernel/cpu/scattered.c
> +++ b/arch/x86/kernel/cpu/scattered.c
> @@ -34,6 +34,9 @@ void init_scattered_cpuid_features(struct cpuinfo_x86 *c)
> { X86_FEATURE_INTEL_PT, CR_EBX,25, 0x00000007, 0 },
> { X86_FEATURE_APERFMPERF, CR_ECX, 0, 0x00000006, 0 },
> { X86_FEATURE_EPB, CR_ECX, 3, 0x00000006, 0 },
> + { X86_FEATURE_CAT_L3, CR_EBX, 1, 0x00000010, 0 },
> + { X86_FEATURE_CAT_L2, CR_EBX, 2, 0x00000010, 0 },
> + { X86_FEATURE_CDP_L3, CR_ECX, 2, 0x00000010, 1 },
> { X86_FEATURE_HW_PSTATE, CR_EDX, 7, 0x80000007, 0 },
> { X86_FEATURE_CPB, CR_EDX, 9, 0x80000007, 0 },
> { X86_FEATURE_PROC_FEEDBACK, CR_EDX,11, 0x80000007, 0 },
> --
--
Regards/Gruss,
Boris.
SUSE Linux GmbH, GF: Felix Imendörffer, Jane Smithard, Graham Norton, HRB 21284
(AG Nürnberg)
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