On 10/21, gabriel.fernan...@st.com wrote:
> From: Gabriel Fernandez <gabriel.fernan...@st.com>
>
> This patch introduces the support of the LSI & LSE clocks.
> The clock drivers needs to disable the power domain write protection
> using syscon/regmap to enable these clocks.
>
> Signed-off-by: Gabriel Fernandez <gabriel.fernan...@st.com>
> ---
Applied to clk-next +
diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c
index c2661e28eeda..5eb05dbf59b8 100644
--- a/drivers/clk/clk-stm32f4.c
+++ b/drivers/clk/clk-stm32f4.c
@@ -224,7 +224,7 @@ static const u64 stm32f46xx_gate_map[MAX_GATE_MAP] = {
0x000000f17ef417ffull,
0x0000000000000003ull,
0x0c777f33f6fec9ffull };
-const u64 *stm32f4_gate_map;
+static const u64 *stm32f4_gate_map;
static struct clk_hw **clks;
--
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