On 11/03, Sricharan wrote: > Ok, so the video ip core, has a hw control signal/bit. > I checked this by dumping this out that, the moment the > gdsc is put to hw control, the video ip's hw control bit also > gets asserted/set. so this means that video ip's bit get > aligned with the gdsc setting. so this should avoid the > glitches, right ? >
Yes that matches my understanding. Thanks for confirming. -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project
