Add phy-pcie node for using Exynos5440 pcie.
And some properies are changed to generic usage.
Signed-off-by: Jaehoon Chung <jh80.ch...@samsung.com>
---
arch/arm/boot/dts/exynos5440.dtsi | 44 ++++++++++++++++++++++++++++++---------
1 file changed, 34 insertions(+), 10 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5440.dtsi
b/arch/arm/boot/dts/exynos5440.dtsi
index 2a2e570..deb2504 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -290,11 +290,34 @@
clock-names = "usbhost";
};
+ pcie_phy0: pcie-phy@270000 {
+ #phy-cells = <0>;
+ compatible = "samsung,exynos5440-pcie-phy";
+ reg = <0x270000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ block@271000 {
+ reg = <0x271000 0x40>;
+ };
+ };
+
+ pcie_phy1: pcie-phy@272000 {
+ #phy-cells = <0>;
+ compatible = "samsung,exynos5440-pcie-phy";
+ reg = <0x272000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ block@271040 {
+ reg = <0x271040 0x40>;
+ };
+ };
+
pcie_0: pcie@290000 {
compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
- reg = <0x290000 0x1000
- 0x270000 0x1000
- 0x271000 0x40>;
+ reg = <0x290000 0x1000>, <0x40000000 0x1000>;
+ reg-names = "elbi", "config";
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
@@ -303,8 +326,9 @@
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
- ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000 /*
configuration space */
- 0x81000000 0 0 0x40001000 0 0x00010000 /*
downstream I/O */
+ pyhs = <&pcie_phy0>;
+ phys = "pcie-phy";
+ ranges = <0x81000000 0 0 0x40001000 0 0x00010000 /*
downstream I/O */
0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /*
non-prefetchable memory */
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
@@ -315,9 +339,8 @@
pcie_1: pcie@2a0000 {
compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
- reg = <0x2a0000 0x1000
- 0x272000 0x1000
- 0x271040 0x40>;
+ reg = <0x2a0000 0x1000>, <0x60000000 0x1000>;
+ reg-names = "elbi", "config";
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
@@ -326,8 +349,9 @@
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
- ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000 /*
configuration space */
- 0x81000000 0 0 0x60001000 0 0x00010000 /*
downstream I/O */
+ pyhs = <&pcie_phy1>;
+ phys = "pcie-phy";
+ ranges = <0x81000000 0 0 0x60001000 0 0x00010000 /*
downstream I/O */
0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /*
non-prefetchable memory */
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
--
2.10.2
