Am Donnerstag, 29. Dezember 2016, 10:45:10 CET schrieb Elaine Zhang: > The rk3328's pll and clock are similar with rk3036's, > it different with pll_mode_mask, the rk3328 soc > pll mode only one bit(rk3036 soc have two bits) > so these should be independent and separate from > the series of rk3328s. > > Changes in v4: > adjust the pacth 3 and 4 order. > move pll_rk3328 to patch 3. > Changes in v3: > fix up the pll type pll_rk3328 description and use > > Signed-off-by: Elaine Zhang <zhangq...@rock-chips.com>
applied to my clk-branch for 4.11 The clock controller itself also looks good now, I'll just give Rob or someone else a bit of time for eventual comments after new years :-) Heiko
