On Wed, Jan 04, 2017 at 05:49:05PM +0000, Suzuki K. Poulose wrote: > Track the user visible fields of a CPU feature register. This will be > used for exposing the value to the userspace. All the user visible > fields of a feature register will be passed on as it is, while the > others would be filled with their respective safe value. > > Cc: Catalin Marinas <[email protected]> > Cc: Will Deacon <[email protected]> > Cc: Mark Rutland <[email protected]> > Signed-off-by: Suzuki K Poulose <[email protected]>
Reviewed-by: Catalin Marinas <[email protected]> > @@ -81,75 +82,75 @@ cpufeature_pan_not_uao(const struct > arm64_cpu_capabilities *entry, int __unused) > > > static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { > - ARM64_FTR_BITS(FTR_STRICT, FTR_EXACT, ID_AA64ISAR0_RDM_SHIFT, 4, 0), > - ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, > 4, 0), > - ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, > 0), > - ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, > 0), > - ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, > 0), > - ARM64_FTR_BITS(FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, > 0), > + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, > ID_AA64ISAR0_RDM_SHIFT, 4, 0), > + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, > ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0), > + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, > ID_AA64ISAR0_CRC32_SHIFT, 4, 0), > + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, > ID_AA64ISAR0_SHA2_SHIFT, 4, 0), > + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, > ID_AA64ISAR0_SHA1_SHIFT, 4, 0), > + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, > ID_AA64ISAR0_AES_SHIFT, 4, 0), BTW, as a separate patch I think we need to expose the RDM field in this register as well, together with a corresponding HWCAP bit. -- Catalin
