Hi Alexandre, > -----Original Message----- > From: Alexandre Belloni [mailto:[email protected]] > Sent: 2017年1月6日 17:05 > To: Wenyou Yang - A41535 <[email protected]> > Cc: Russell King <[email protected]>; Nicolas Ferre > <[email protected]>; Rob Herring <[email protected]>; Mark Rutland > <[email protected]>; [email protected]; Wenyou Yang - A41535 > <[email protected]>; [email protected]; linux-arm- > [email protected] > Subject: Re: [PATCH 1/3] ARM: at91: flush the L2 cache before entering cpu > idle > > Hi, > > On 06/01/2017 at 14:59:45 +0800, Wenyou Yang wrote : > > For the SoCs such as SAMA5D2 and SAMA5D4 which have L2 cache, flush > > the L2 cache first before entering the cpu idle. > > > > Signed-off-by: Wenyou Yang <[email protected]> > > --- > > > > arch/arm/mach-at91/pm.c | 19 +++++++++++++++++++ > > drivers/memory/atmel-sdramc.c | 1 + > > 2 files changed, 20 insertions(+) > > > > diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c index > > b4332b727e9c..1a60dede1a01 100644 > > --- a/arch/arm/mach-at91/pm.c > > +++ b/arch/arm/mach-at91/pm.c > > @@ -289,6 +289,24 @@ static void at91_ddr_standby(void) > > at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1); } > > > > +static void at91_ddr_cache_standby(void) { > > + u32 saved_lpr; > > + > > + flush_cache_all(); > > + outer_disable(); > > + > > + saved_lpr = at91_ramc_read(0, AT91_DDRSDRC_LPR); > > + at91_ramc_write(0, AT91_DDRSDRC_LPR, (saved_lpr & > > + (~AT91_DDRSDRC_LPCB)) | > AT91_DDRSDRC_LPCB_SELF_REFRESH); > > + > > + cpu_do_idle(); > > + > > + at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr); > > + > > + outer_resume(); > > +} > > + > > Seems good to me. Did you measure the added latency on sama5d3 if you add the > cache operations in at91_ddr_standby instead of having a new function?
No, I didn't. How to measure it? Best Regards, Wenyou Yang
