> Quoting Eric W. Biederman <[EMAIL PROTECTED]>: > Subject: Re: SATA resume slowness, e1000 MSI warning > > "Michael S. Tsirkin" <[EMAIL PROTECTED]> writes: > > >> Rumor has it that some pci devices can't tolerate < 32bit accesses. > >> Although I have never met one. > > > > hopefully not bridge devices? > > > >> The two factors together suggest that > >> for generic code it probably makes sense to operate on 32bit > >> quantities, and just to ignore the read-only portion. > > > > The code for regular devices seems to use 16-bit accesses, so > > I think it's best to stay consistent. Or do you want to change this too? > > If we are stomping rare probabilities we might as well change that too. > The code to save pci-x state is relatively recent. So it probably just > hasn't met a problem device yet (assuming they exist).
OK I guess. I gather we assume writing read-only registers has no side effects? Are there rumors circulating wrt to these? -- MST - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to [EMAIL PROTECTED] More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
