Hi Stephen, On 1/20/2017 11:12 PM, Stephen Boyd wrote:
Thanks for the review. Yes, I have addressed this comment on top of this series along with one other fix.On 01/09/2017 11:00 PM, Ritesh Harjani wrote:From: Subhash Jadavani <[email protected]>Program CORE_CSR_CDC_DELAY_CFG for hardware recommended 1.25ns delay. We may see data CRC errors if it's programmed for any other delay value. Signed-off-by: Subhash Jadavani <[email protected]> Signed-off-by: Ritesh Harjani <[email protected]> --- drivers/mmc/host/sdhci-msm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index a028568..84d29dd 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -679,7 +679,7 @@ static int sdhci_msm_cdclp533_calibration(struct sdhci_host *host) writel_relaxed(0x4, host->ioaddr + CORE_CSR_CDC_CAL_TIMER_CFG1); writel_relaxed(0xCB732020, host->ioaddr + CORE_CSR_CDC_REFCOUNT_CFG); writel_relaxed(0xB19, host->ioaddr + CORE_CSR_CDC_COARSE_CAL_CFG); - writel_relaxed(0x3AC, host->ioaddr + CORE_CSR_CDC_DELAY_CFG); + writel_relaxed(0x4E2, host->ioaddr + CORE_CSR_CDC_DELAY_CFG); writel_relaxed(0x0, host->ioaddr + CORE_CDC_OFFSET_CFG); writel_relaxed(0x16334, host->ioaddr + CORE_CDC_SLAVE_DDA_CFG);There's a comment block above this set of writes that repeats what's happening in the code. /* * Perform CDC Register Initialization Sequence * * CORE_CSR_CDC_CTLR_CFG0 0x11800EC * CORE_CSR_CDC_CTLR_CFG1 0x3011111 * CORE_CSR_CDC_CAL_TIMER_CFG0 0x1201000 * CORE_CSR_CDC_CAL_TIMER_CFG1 0x4 * CORE_CSR_CDC_REFCOUNT_CFG 0xCB732020 * CORE_CSR_CDC_COARSE_CAL_CFG 0xB19 * CORE_CSR_CDC_DELAY_CFG 0x3AC * CORE_CDC_OFFSET_CFG 0x0 * CORE_CDC_SLAVE_DDA_CFG 0x16334 */ Perhaps we should just delete those comments because they're incorrect now.
-named ("mmc: sdhci-msm: Addresses minor cleanups")
Regards
Ritesh
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