Peter,
On 1/25/17 16:46, Peter Zijlstra wrote:
On Mon, Jan 16, 2017 at 01:23:36AM -0600, Suravee Suthikulpanit wrote:
+ pi = container_of(event->pmu, struct perf_amd_iommu, pmu);
+ hwc->idx = pi->idx;
+ hwc->config = event->attr.config;
+ hwc->extra_reg.config = event->attr.config1;
static void perf_iommu_enable_event(struct perf_event *ev)
{
+ struct hw_perf_event *hwc = &ev->hw;
u8 csource = _GET_CSOURCE(ev);
u16 devid = _GET_DEVID(ev);
u8 bank = _GET_BANK(ev);
@@ -253,30 +248,34 @@ static void perf_iommu_enable_event(struct perf_event *ev)
u64 reg = 0ULL;
reg = csource;
- amd_iommu_pc_set_reg(0, bank, cntr,
+ amd_iommu_pc_set_reg(hwc->idx, bank, cntr,
IOMMU_PC_COUNTER_SRC_REG, ®);
Please explain about this IOMMU crud, this looks like fail.
hwc->idx should be the counter, not a random pmu index.
Ok, I thought this was not used by the code, so I used it for
holding PMU index. This might not be a good idea.
I will change this part per Boris comment in the reply of this
thread.
But instead it looks like you get the counter form:
#define _GET_CNTR(ev) ((u8)(ev->hw.extra_reg.reg))
Which is absolutely insane.
So, the IOMMU counters are grouped into bank, and there could be
many banks. I use the extra_reg.reg to hold the bank and counter
indices. This will be used to program onto the counter configuration
register. This is handled in get_next_avail_iommu_bnk_cntr() and
clear_avail_iommu_bnk_cntr().
Thanks,
Suravee
