From: Thierry Reding <tred...@nvidia.com> Hi everyone,
This series of patches start with a few cleanups that I ran across while adding Tegra186 support to the stmmac driver. It then adds code for FIFO size parsing from feature registers and finally enables support for the incarnation of the Synopsys DWC QOS IP found on NVIDIA Tegra186 SoCs. This is based on next-20170223. Thanks, Thierry Thierry Reding (7): net: stmmac: Rename clk_ptp_ref clock to ptp_ref net: stmmac: Balance PTP reference clock enable/disable net: stmmac: Check for DMA mapping errors net: stmmac: Parse FIFO sizes from feature registers net: stmmac: Program RX queue size and flow control net: stmmac: dwc-qos: Split out ->probe() and ->remove() net: stmmac: dwc-qos: Add Tegra186 support Documentation/devicetree/bindings/net/stmmac.txt | 6 +- drivers/net/ethernet/stmicro/stmmac/common.h | 3 + .../ethernet/stmicro/stmmac/dwmac-dwc-qos-eth.c | 366 +++++++++++++++++++-- drivers/net/ethernet/stmicro/stmmac/dwmac4.h | 12 + drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c | 45 ++- drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 9 + .../net/ethernet/stmicro/stmmac/stmmac_platform.c | 3 +- 7 files changed, 411 insertions(+), 33 deletions(-) -- 2.11.1
