Series, Reviewed-by: Mikko Perttunen <mperttu...@nvidia.com> Tested-by: Mikko Perttunen <mperttu...@nvidia.com>
On 02/23/2017 12:44 PM, Peter De Schrijver wrote:
A number of bug fixes for the Tegra210 clock implementation. Changelog: v2: add better description for 'remove non-existing pll_m_out1 clock' Peter De Schrijver (7): clk: tegra: fix pll_a1 iddq register, add pll_a1 clk: tegra: fix isp clock modelling clk: tegra: correct afi parent clk: tegra: remove non-existing pll_m_out1 clock clk: tegra: don't warn for PLL defaults unnecessarily clk: tegra: correct tegra210_pll_fixed_mdiv_cfg rate calculation clk: tegra: fix type for m field drivers/clk/tegra/clk-id.h | 1 + drivers/clk/tegra/clk-tegra-periph.c | 13 +++++++++--- drivers/clk/tegra/clk-tegra210.c | 35 ++++++++++++++++++++------------ drivers/clk/tegra/clk.h | 2 +- include/dt-bindings/clock/tegra210-car.h | 4 ++-- 5 files changed, 36 insertions(+), 19 deletions(-)
