On Tue, Feb 28, 2017 at 04:35:31PM +0800, Icenowy Zheng wrote: > > > 28.02.2017, 14:43, "Maxime Ripard" <maxime.rip...@free-electrons.com>: > > On Tue, Feb 28, 2017 at 03:27:14AM +0800, Icenowy Zheng wrote: > >> The H3 SoC have a bigger SID controller, which has its direct read > >> address at 0x200 position in the SID block, not 0x0. > >> > >> Also, H3 SID controller has some silicon bug that makes the direct read > >> value wrong at cold boot, add code to workaround the bug. (This bug has > >> already been fixed on A64 and later SoCs) > >> > >> Signed-off-by: Icenowy Zheng <icen...@aosc.xyz> > > > > Acked-by: Maxime Ripard <maxime.rip...@free-electrons.com> > > Who will finally apply these patches? > > I have seen that you are one of the maintainers of NVMEM subsystem.
Srinivas usually merges the patches. Maxime -- Maxime Ripard, Free Electrons Embedded Linux and Kernel engineering http://free-electrons.com
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