On Thu, Apr 13, 2017 at 8:28 PM, Shawn Guo <[email protected]> wrote: > On Thu, Apr 13, 2017 at 06:32:37AM -0700, Andrey Smirnov wrote: >> In PMU_REG_1P0Dn ENABLE_LINREG is bit 0. Bit 31 is called OVERRIDE and >> it serves the function of granting permission to GPC IP block to alter >> various bit-fields of the register. The reason why this property, that >> trickeld here from Freescale BSP, is set to 31 is because in the code >> it came from it is used in conjunction with a notifier handler for >> REGULATOR_EVENT_PRE_DO_ENABLE and REGULATOR_EVENT_PRE_DO_DISABLE >> events (not found in upstream kernel) that triggers GPC to start >> manipulating aforementioned other bitfields. >> >> Since: >> a) none of the aforementioned machinery is implemented by >> upstream >> b) using 'anatop-enable-bit' in that capacity is a bit of a >> semantic stretch >> >> simplify the situation by setting the value of 'anatop-enable-bit' to >> point to ENABLE_LINREG (same as i.MX6). >> >> Cc: [email protected] >> Cc: Sascha Hauer <[email protected]> >> Cc: Fabio Estevam <[email protected]> >> Cc: Rob Herring <[email protected]> >> Cc: Mark Rutland <[email protected]> >> Cc: Russell King <[email protected]> >> Cc: [email protected] >> Cc: [email protected] >> Cc: [email protected] >> Signed-off-by: Andrey Smirnov <[email protected]> > > Since patch 1 ~ 3 are all about adding anatop-enable-bit, can we squash > them into one patch?
OK. Will do in v2.
