From: gabriele paoloni <gabriele.paol...@huawei.com>
Currently the MSI/MSIx vectors for the root port services are
allocated calling pcie_init_service_irqs(). At the moment these
vectors are only allocated for AER, PME, HP.
This patch allocate an MSI/MSIx vector also for DPC.
Signed-off-by: Liudongdong <liudongdo...@huawei.com>
Signed-off-by: Gabriele Paoloni <gabriele.paol...@huawei.com>
---
drivers/pci/pcie/portdrv_core.c | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/drivers/pci/pcie/portdrv_core.c b/drivers/pci/pcie/portdrv_core.c
index 254bc73..4a8a1df 100644
--- a/drivers/pci/pcie/portdrv_core.c
+++ b/drivers/pci/pcie/portdrv_core.c
@@ -126,6 +126,31 @@ static int pcie_port_enable_irq_vec(struct pci_dev *dev,
int *irqs, int mask)
nvec = max(nvec, entry + 1);
}
+ if (mask & PCIE_PORT_SERVICE_DPC) {
+ u16 reg16, pos;
+
+ /*
+ * The code below follows Section 6.2.10.1 of the PCI Express
+ * Base Specification 4.0 stating that bits 4-0 of DPC
+ * Capability Register contain a value indicating which of the
+ * MSI/MSI-X vectors assigned to the port is going to be used
+ * for DPC, where "For MSI-X, the value in this register
+ * indicates which MSI-X Table entry is used to generate the
+ * interrupt message." and "For MSI, the value in this field
+ * indicates the offset between the base Message Data and the
+ * interrupt message that is generated."
+ */
+ pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DPC);
+ pci_read_config_word(dev, pos + PCI_EXP_DPC_CAP, ®16);
+ entry = reg16 & 0x1f;
+ if (entry >= nr_entries)
+ goto out_free_irqs;
+
+ irqs[PCIE_PORT_SERVICE_DPC_SHIFT] = pci_irq_vector(dev, entry);
+
+ nvec = max(nvec, entry + 1);
+ }
+
/*
* If nvec is equal to the allocated number of entries, we can just use
* what we have. Otherwise, the port has some extra entries not for the
--
2.7.4
