> +     /*
> +      * DMA is based on a 16MHz clock
> +      */
> +     if (ata_timing_compute(adev, adev->dma_mode, &t, 1000, 1))
> +             return;

This seems strange for a 16MHz clock.

> +
> +     /*
> +      * Now, properly adjust the timings.  If we have a 62.5ns clock
> +      * period and we ask for MWDMA2, it calculates the following
> +      * timings: active 125ns, recovery 62.5ns, cycle 125ns.
> +      * Quite obviously bogus. 

NAK. 

At this point you need to work out why you are getting bogus results and
fix it or demonstrate a bug in the core code and fix that.

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