On Tue, Aug 01, 2017 at 06:48:20PM +0200, Peter Zijlstra wrote: > On Tue, Aug 01, 2017 at 05:44:14PM +0100, Will Deacon wrote: > > On Tue, Aug 01, 2017 at 06:39:03PM +0200, Peter Zijlstra wrote: > > > Still this is all rather unsatisfactory. Either we should define > > > flush_tlb*() to imply a barrier when its not a no-op (sparc64/ppc-hash) > > > or simply make clear_tlb_flush_pending() an smp_store_release(). > > > > > > I prefer the latter option. > > > > > > Opinions? > > > > I prefer the latter option too, since I'd like to relax the arm64 TLB > > flushing to have weaker barriers for the local case. Granted, that doesn't > > break the NUMA migration code, but it would make the barrier semantics of > > the TLB invalidation routines even more subtle if we were to define them > > generally. > > Another 'fun' question, is smp_mb() strong enough to order against the > TLB invalidate? Because we really want to clear this flag _after_. > > PowerPC for example uses PTESYNC before the TBLIE, so does a SYNC after > work? Ben?
>From what I gather it is not. You have TLBSYNC for it. So the good news is that PPC-radix does all that and is fully serialized on the tlb flush. Not sure for the PPC-hash case. At the same time, smp_mb() is not sufficient on ARM either, they need a DSB barrier on both ends. So are we going to mandate tlb flush implementations are completely ordered ?
