Commit-ID: 18416e45b76189daf37ba53b2bd0b9ac3749e92e Gitweb: http://git.kernel.org/tip/18416e45b76189daf37ba53b2bd0b9ac3749e92e Author: Marc Zyngier <marc.zyng...@arm.com> AuthorDate: Fri, 18 Aug 2017 09:39:24 +0100 Committer: Thomas Gleixner <t...@linutronix.de> CommitDate: Fri, 18 Aug 2017 10:54:43 +0200
irqchip/mips-gic: Report that effective affinity is a single target The MIPS GIC driver only targets a single CPU at a time, even if the notional affinity is wider. Let's inform the core code about this. Signed-off-by: Marc Zyngier <marc.zyng...@arm.com> Signed-off-by: Thomas Gleixner <t...@linutronix.de> Cc: Andrew Lunn <and...@lunn.ch> Cc: James Hogan <james.ho...@imgtec.com> Cc: Jason Cooper <ja...@lakedaemon.net> Cc: Paul Burton <paul.bur...@imgtec.com> Cc: Chris Zankel <ch...@zankel.net> Cc: Kevin Cernekee <cerne...@gmail.com> Cc: Wei Xu <xuw...@hisilicon.com> Cc: Max Filippov <jcmvb...@gmail.com> Cc: Florian Fainelli <f.faine...@gmail.com> Cc: Gregory Clement <gregory.clem...@free-electrons.com> Cc: Matt Redfearn <matt.redfe...@imgtec.com> Cc: Sebastian Hesselbarth <sebastian.hesselba...@gmail.com> Link: http://lkml.kernel.org/r/20170818083925.10108-12-marc.zyng...@arm.com --- drivers/irqchip/Kconfig | 1 + drivers/irqchip/irq-mips-gic.c | 10 +++++++--- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 39bfa5b..bca9a88 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -141,6 +141,7 @@ config IRQ_MIPS_CPU select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING select IRQ_DOMAIN select IRQ_DOMAIN_HIERARCHY if GENERIC_IRQ_IPI + select GENERIC_IRQ_EFFECTIVE_AFF_MASK config CLPS711X_IRQCHIP bool diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c index 6ab1d3a..6461380 100644 --- a/drivers/irqchip/irq-mips-gic.c +++ b/drivers/irqchip/irq-mips-gic.c @@ -445,24 +445,27 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask, unsigned int irq = GIC_HWIRQ_TO_SHARED(d->hwirq); cpumask_t tmp = CPU_MASK_NONE; unsigned long flags; - int i; + int i, cpu; cpumask_and(&tmp, cpumask, cpu_online_mask); if (cpumask_empty(&tmp)) return -EINVAL; + cpu = cpumask_first(&tmp); + /* Assumption : cpumask refers to a single CPU */ spin_lock_irqsave(&gic_lock, flags); /* Re-route this IRQ */ - gic_map_to_vpe(irq, mips_cm_vp_id(cpumask_first(&tmp))); + gic_map_to_vpe(irq, mips_cm_vp_id(cpu)); /* Update the pcpu_masks */ for (i = 0; i < min(gic_vpes, NR_CPUS); i++) clear_bit(irq, pcpu_masks[i].pcpu_mask); - set_bit(irq, pcpu_masks[cpumask_first(&tmp)].pcpu_mask); + set_bit(irq, pcpu_masks[cpu].pcpu_mask); cpumask_copy(irq_data_get_affinity_mask(d), cpumask); + irq_data_update_effective_affinity(d, cpumask_of(cpu)); spin_unlock_irqrestore(&gic_lock, flags); return IRQ_SET_MASK_OK_NOCOPY; @@ -716,6 +719,7 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int virq, if (err) return err; + irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq))); return gic_shared_irq_domain_map(d, virq, hwirq, 0); }
