----- On Aug 28, 2017, at 1:12 PM, Max Filippov jcmvb...@gmail.com wrote: > Hi Mathieu, > > On Mon, Aug 28, 2017 at 12:36 AM, Mathieu Desnoyers > <mathieu.desnoy...@efficios.com> wrote: >> The membarrier system call now requires all architectures to implement >> sync_core(). On Xtensa, it is provided by the EXTW instruction. >> >> [ Completely untested! Can someone on the xtensa side confirm whether >> EXTW is the right way to serialize core execution and try it out ? ] > > Thanks for the patch. I'm currently travelling, I'll give it a try next week > once I'm back at work.
Hi Max, I think we may need to flush the icache to make it consistent with the dcache too on xtensa, in addition to the EXTW. The goal here is to allow JIT engines to reclaim and re-use memory after they discard dynamically generated code. This is similar to what we'd need to do on arm32, where they have inconsistent d/i-caches. Thoughts ? Thanks, Mathieu > > -- > Thanks. > -- Max -- Mathieu Desnoyers EfficiOS Inc. http://www.efficios.com
