* Kishon Vijay Abraham I <kis...@ti.com> [171222 06:06]:
> Hi Rob,
>
> On Thursday 21 December 2017 12:27 AM, Rob Herring wrote:
> > On Tue, Dec 19, 2017 at 02:28:22PM +0530, Kishon Vijay Abraham I wrote:
> >> Add syscon properties required for configuring PCIe in x2 lane mode.
> >>
> >> Signed-off-by: Kishon Vijay Abraham I <kis...@ti.com>
> >> Signed-off-by: Sekhar Nori <nsek...@ti.com>
> >> ---
> >> Documentation/devicetree/bindings/pci/ti-pci.txt | 6 ++++++
> >> 1 file changed, 6 insertions(+)
> >>
> >> diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt
> >> b/Documentation/devicetree/bindings/pci/ti-pci.txt
> >> index 82cb875e4cec..bfbc77ac7355 100644
> >> --- a/Documentation/devicetree/bindings/pci/ti-pci.txt
> >> +++ b/Documentation/devicetree/bindings/pci/ti-pci.txt
> >> @@ -13,6 +13,12 @@ PCIe DesignWare Controller
> >> - ti,hwmods : Name of the hwmod associated to the pcie, "pcie<X>",
> >> where <X> is the instance number of the pcie from the HW spec.
> >> - num-lanes as specified in ../designware-pcie.txt
> >> + - ti,syscon-lane-conf : phandle/offset pair. Phandle to the system
> >> control
> >> + module and the register offset to specify 1 lane or
> >> + 2 lane.
> >> + - ti,syscon-lane-sel : phandle/offset pair. Phandle to the system control
> >> + module and the register offset to specify lane
> >> + selection.
> >
> > Adding a property for every syscon register doesn't really scale and
> > doesn't work if the register layout changes.
>
> The register layout doesn't really change between silicon revisions and for
> new
> SoCs, the phandle and the register offset for that SoC will have to be
> populated again.
>
> Having said that, I'm not aware of any other alternative here.
Sorry I did not realize this is still open. Sounds like I need to
revert commit 4ece93c020e3 ("ARM: dts: dra7: Add properties to
enable PCIe x2 lane mode"), let me know if that is not the case.
Regards,
Tony
